The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 20, 2022
Filed:
Apr. 16, 2019
Intel Corporation, Santa Clara, CA (US);
Han Wui Then, Portland, OR (US);
Robert Chau, Beaverton, OR (US);
Valluri Rao, Saratoga, CA (US);
Niloy Mukherjee, San Ramon, CA (US);
Marko Radosavljevic, Portland, OR (US);
Ravi Pillarisetty, Portland, OR (US);
Gilbert Dewey, Beaverton, OR (US);
Jack Kavalieros, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Fand also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.