The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 20, 2022
Filed:
Nov. 30, 2020
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Su-Hao Liu, Jhongpu Township, TW;
Tsan-Chun Wang, Hsinchu, TW;
Liang-Yin Chen, Hsinchu, TW;
Jing-Huei Huang, Yuanshan Township, TW;
Lun-Kuang Tan, Hsinchu, TW;
Huicheng Chang, Tainan, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-chu, TW;
Abstract
In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.