The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2022

Filed:

Jun. 29, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Lai Guan Tang, Penang, MY;

Ankireddy Nalamalpu, Portland, OR (US);

Dheeraj Subbareddy, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/07 (2006.01); H03L 7/087 (2006.01); H03L 7/093 (2006.01); G06F 1/12 (2006.01); H01L 25/065 (2006.01); H01L 23/538 (2006.01); H03L 7/099 (2006.01); H03L 7/06 (2006.01); H03L 7/22 (2006.01);
U.S. Cl.
CPC ...
H03L 7/07 (2013.01); G06F 1/12 (2013.01); H01L 23/5381 (2013.01); H01L 23/5385 (2013.01); H01L 25/0655 (2013.01); H03L 7/06 (2013.01); H03L 7/087 (2013.01); H03L 7/093 (2013.01); H03L 7/099 (2013.01); H03L 7/22 (2013.01);
Abstract

An IC, operable at a first clock phase, includes first and second IOs and a PLL. The PLL includes a control circuit, an input to receive a first clock signal, an output to output a second clock signal, and a first detector to generate a first phase difference signal from the first and second clock signals. The IC includes a second phase detector that is coupled to the PLL's output to receive the second clock signal and is coupled to the first IO to receive a third clock single from a second IC, which is operable at a second clock phase. The second detector generates a second phase difference signal from the second and third clock signals. If the PLL uses the second phase difference signal to generate the second clock signal, then the second clock signal is synchronized with the third clock signal for synchronous data transfer.


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