The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2022
Filed:
Oct. 24, 2019
Applicant:
Applied Materials, Inc., Santa Clara, CA (US);
Inventors:
Hao Jiang, San Jose, CA (US);
Chi Lu, Sunnyvale, CA (US);
He Ren, San Jose, CA (US);
Chi-I Lang, Cupertino, CA (US);
Ho-yung David Hwang, Cupertino, CA (US);
Mehul Naik, San Jose, CA (US);
Assignee:
Applied Materials, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/027 (2006.01); H01L 21/3213 (2006.01); H01L 21/306 (2006.01); H01L 21/203 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/0276 (2013.01); H01L 21/203 (2013.01); H01L 21/30621 (2013.01); H01L 21/32135 (2013.01); H01L 21/76834 (2013.01);
Abstract
A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.