The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

Mar. 28, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jeffrey Chromczak, Toronto, CA;

Chooi Pei Lim, Penang, MY;

Lai Guan Tang, Penang, MY;

Chee Hak Teh, Penang, MY;

MD Altaf Hossain, Portland, OR (US);

Dheeraj Subbareddy, Portland, OR (US);

Ankireddy Nalamalpu, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); H01L 23/3114 (2013.01); H01L 23/5381 (2013.01); H01L 24/14 (2013.01); H01L 24/16 (2013.01); H01L 2224/14131 (2013.01); H01L 2224/14133 (2013.01); H01L 2224/14515 (2013.01); H01L 2224/16227 (2013.01);
Abstract

A circuit system includes an interposer that has a first clock network and first and second integrated circuit dies that are mounted on the interposer. The first integrated circuit die includes a phase detector circuit, an adjustable delay circuit that generates a second clock signal in response to a first clock signal received from the first clock network, and a second clock network that generates a third clock signal in response to the second clock signal. The second integrated circuit die comprises a third clock network that generates a fourth clock signal in response to the first clock signal received from the first clock network. The phase detector circuit controls a delay provided by the adjustable delay circuit to the second clock signal based on a phase comparison between phases of the third and fourth clock signals.


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