The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2022

Filed:

Nov. 17, 2020
Applicant:

Xintec Inc., Taoyuan, TW;

Inventors:

Yen-Shih Ho, Kaohsiung, TW;

Tsang-Yu Liu, Zhubei, TW;

Po-Han Lee, Taipei, TW;

Assignee:

XINTEC INC., Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14636 (2013.01); H01L 24/02 (2013.01); H01L 27/14618 (2013.01); H01L 27/14632 (2013.01); H01L 27/14685 (2013.01); H01L 27/14687 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 27/1462 (2013.01); H01L 27/14678 (2013.01); H01L 2224/02371 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/02377 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/06131 (2013.01); H01L 2224/06136 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/14131 (2013.01); H01L 2224/14136 (2013.01); H01L 2224/94 (2013.01);
Abstract

A manufacturing method of a chip package includes forming a temporary bonding layer on a carrier; forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer; bonding the carrier to the wafer, in which the encapsulation layer covers a sensor and a conductive pad of the wafer; patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole; forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole; forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole; forming a passivation layer on the isolation layer and the redistribution layer; and removing the temporary bonding layer and the carrier.


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