The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2022

Filed:

Nov. 15, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Min-Feng Kao, Chiayi, TW;

Szu-Ying Chen, Toufen Township, TW;

Dun-Nian Yaung, Taipei, TW;

Jen-Cheng Liu, Hsinchu, TW;

Tzu-Hsuan Hsu, Kaohsiung, TW;

Feng-Chi Hung, Chubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/02 (2006.01); H01L 21/265 (2006.01); H01L 21/762 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 23/544 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 21/2652 (2013.01); H01L 21/28114 (2013.01); H01L 21/76229 (2013.01); H01L 23/544 (2013.01); H01L 27/1464 (2013.01); H01L 27/14609 (2013.01); H01L 29/42376 (2013.01); H01L 29/665 (2013.01); H01L 29/6659 (2013.01); H01L 29/7833 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54453 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the first portion and the second portion of the gate electrode.


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