The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2022
Filed:
Jul. 24, 2018
Intel Corporation, Santa Clara, CA (US);
Abhishek A. Sharma, Hillsboro, OR (US);
Juan G. Alzate-Vinasco, Tigard, OR (US);
Fatih Hamzaoglu, Portland, OR (US);
Bernhard Sell, Portland, OR (US);
Pei-hua Wang, Beaverton, OR (US);
Van H. Le, Beaverton, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Tahir Ghani, Portland, OR (US);
Umut Arslan, Portland, OR (US);
Travis W. Lajoie, Forest Grove, OR (US);
Chieh-jen Ku, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Described herein are arrays of embedded dynamic random-access memory (eDRAM) cells that use TFTs as selector transistors. When at least some selector transistors are implemented as TFTs, different eDRAM cells may be provided in different layers above a substrate, enabling a stacked architecture. An example stacked TFT based eDRAM includes one or more memory cells provided in a first layer over a substrate and one or more memory cells provided in a second layer, above the first layer, where at least the memory cells in the second layer, but preferably the memory cells in both the first and second layers, use TFTs as selector transistors. Stacked TFT based eDRAM allows increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.