The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2022

Filed:

Jul. 02, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Van H. Le, Portland, OR (US);

Benjamin Chu-Kung, Portland, OR (US);

Willy Rachmady, Beaverton, OR (US);

Marc C. French, Forest Grove, OR (US);

Seung Hoon Sung, Portland, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Matthew V. Metz, Portland, OR (US);

Ashish Agrawal, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02532 (2013.01); H01L 21/02381 (2013.01); H01L 29/1054 (2013.01); H01L 29/6681 (2013.01); H01L 29/66818 (2013.01); H01L 29/785 (2013.01);
Abstract

An apparatus including a transistor device including a channel including germanium disposed on a substrate; a buffer layer disposed on the substrate between the channel and the substrate, wherein the buffer layer includes silicon germanium; and a seed layer disposed on the substrate between the buffer layer and the substrate, wherein the seed layer includes germanium. A method including forming seed layer on a silicon substrate, wherein the seed layer includes germanium; forming a buffer layer on the seed layer, wherein the buffer layer includes silicon germanium; and forming a transistor device including a channel on the buffer layer.


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