The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2022

Filed:

Dec. 20, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tai-I Yang, Hsinchu, TW;

Wei-Chen Chu, Taichung, TW;

Hsiang-Wei Liu, Tainan, TW;

Shau-Lin Shue, Hsinchu, TW;

Li-Lin Su, Taichung County, TW;

Yung-Hsu Wu, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 7/20 (2006.01); H01L 21/768 (2006.01); G03F 7/004 (2006.01); G03F 7/00 (2006.01); G03F 7/09 (2006.01);
U.S. Cl.
CPC ...
G03F 7/70633 (2013.01); G03F 7/0035 (2013.01); G03F 7/0043 (2013.01); G03F 7/0047 (2013.01); G03F 7/094 (2013.01); G03F 7/70625 (2013.01); H01L 21/7682 (2013.01); H01L 21/76807 (2013.01); H01L 21/76837 (2013.01); H01L 21/76885 (2013.01); H01L 21/76897 (2013.01); H01L 21/76849 (2013.01);
Abstract

Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.


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