The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2022
Filed:
Jun. 09, 2020
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Kuo-Ming Wu, Zhubei, TW;
Ching-Chun Wang, Tainan, TW;
Dun-Nian Yaung, Taipei, TW;
Hsing-Chih Lin, Tainan, TW;
Jen-Cheng Liu, Hsin-Chu, TW;
Min-Feng Kao, Chiayi, TW;
Yung-Lung Lin, Taichung, TW;
Shih-Han Huang, Kaohsiung, TW;
I-Nan Chen, Taipei, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
A method for manufacturing three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is formed and bonded to a first IC die by a first bonding structure. A third IC die is formed and bonded to the second IC die by a second bonding structure. The second bonding structure is formed between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. In some further embodiments, the second bonding structure is formed by forming conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.