The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2022

Filed:

May. 07, 2021
Applicant:

Unimicron Technology Corp., Taoyuan, TW;

Inventors:

John Hon-Shing Lau, Taoyuan, TW;

Cheng-Ta Ko, Taipei, TW;

Pu-Ju Lin, Hsinchu, TW;

Tzyy-Jang Tseng, Taoyuan, TW;

Ra-Min Tain, Hsinchu County, TW;

Kai-Ming Yang, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5384 (2013.01); H01L 21/486 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/14505 (2013.01); H01L 2224/16227 (2013.01);
Abstract

A package structure, including a bridge, an interposer, a first redistribution structure layer, a second redistribution structure layer, and multiple chips, is provided. The bridge includes a silicon substrate, a redistribution layer, and multiple bridge pads. The interposer includes an intermediate layer, multiple conductive vias, multiple first pads, and multiple second pads. The bridge is embedded in the intermediate layer. The bridge pads are aligned with the upper surface. The first redistribution structure layer is disposed on the upper surface of the interposer and is electrically connected to the first pads and the bridge pads. The second redistribution structure layer is disposed on the lower surface of the interposer and is electrically connected to the second pads. The chips are disposed on the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The chips are electrically connected to each other through the bridge.


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