The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 2022
Filed:
Jun. 22, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Bruce E. Beattie, Portland, OR (US);
Leonard Guler, Hillsboro, OR (US);
Biswajeet Guha, Hillsboro, OR (US);
Jun Sung Kang, Portland, OR (US);
William Hsu, Hillsboro, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7856 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/42356 (2013.01); H01L 29/6681 (2013.01); H01L 29/66545 (2013.01); H01L 2029/7858 (2013.01);
Abstract
Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant ('low-κ') material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.