The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2022

Filed:

Mar. 23, 2021
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Michael B. Vincent, Chandler, AZ (US);

Scott M. Hayes, Chandler, AZ (US);

Zhiwei Gong, Chandler, AZ (US);

Vivek Gupta, Phoenix, AZ (US);

Richard Te Gan, Chandler, AZ (US);

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 21/67 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/56 (2013.01); H01L 21/67288 (2013.01); H01L 21/78 (2013.01); H01L 23/562 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A method of manufacturing a semiconductor device packaging panel is provided. The method includes forming a panel by placing a plurality of semiconductor die on a major side of a carrier substrate and encapsulating with an encapsulant the plurality semiconductor die and the major side of the carrier substrate. A plurality of warpage control features are formed with the encapsulant while encapsulating. The method further includes placing the panel onto a warpage control fixture to substantially flatten the panel. The plurality of warpage control features interlock with mating features of the warpage control fixture.


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