The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2022

Filed:

May. 21, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ehren Mannebach, Beaverton, OR (US);

Kevin Lin, Beaverton, OR (US);

Richard Vreeland, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 23/522 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5329 (2013.01); H01L 21/7684 (2013.01); H01L 21/76834 (2013.01); H01L 21/76837 (2013.01); H01L 21/76877 (2013.01); H01L 21/823475 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 21/3212 (2013.01);
Abstract

Embodiments include an interconnect structure and methods of forming an interconnect structure. In an embodiment, the interconnect structure comprises a semiconductor substrate and an interlayer dielectric (ILD) over the semiconductor substrate. In an embodiment, an interconnect layer is formed over the ILD. In an embodiment, the interconnect layer comprises a first interconnect and a second interconnect. In an embodiment the interconnect structure comprises an electrically insulating plug that separates the first interconnect and the second interconnect. In an embodiment an uppermost surface of the electrically insulating plug is above an uppermost surface of the interconnect layer.


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