The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2022

Filed:

Jun. 14, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Subramaniam Maiyuran, Gold River, CA (US);

Shubra Marwaha, Folsom, CA (US);

Ashutosh Garg, Folsom, CA (US);

Supratim Pal, Bangalore, IN;

Jorge Parra, El Dorado Hills, CA (US);

Chandra Gurram, Folsom, CA (US);

Varghese George, Folsom, CA (US);

Darin Starkey, Roseville, CA (US);

Guei-Yuan Lueh, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 15/06 (2011.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 17/18 (2006.01);
U.S. Cl.
CPC ...
G06T 15/06 (2013.01); G06F 9/3001 (2013.01); G06F 9/3887 (2013.01); G06F 17/18 (2013.01);
Abstract

Described herein is a graphics processing unit (GPU) comprising a single instruction, multiple thread (SIMT) multiprocessor comprising an instruction cache, a shared memory coupled with the instruction cache, and circuitry coupled with the shared memory and the instruction cache, the circuitry including multiple texture units, a first core including hardware to accelerate matrix operations, and a second core configured to receive an instruction having multiple operands in a bfloat16 (BF16) number format, wherein the multiple operands include a first source operand, a second source operand, and a third source operand, and the BF16 number format is a sixteen-bit floating point format having an eight-bit exponent and process the instruction, wherein to process the instruction includes to multiply the second source operand by the third source operand and add a first source operand to a result of the multiply.


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