The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2022

Filed:

Jan. 10, 2020
Applicant:

Globalfoundries U.s. Inc., Santa Clara, CA (US);

Inventors:

Jiehui Shu, Clifton Park, NY (US);

Haiting Wang, Clifton Park, NY (US);

Hong Yu, Rexford, NY (US);

Assignee:

GLOBALFOUNDRIES U.S. INC., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); H01L 21/76224 (2013.01); H01L 27/0886 (2013.01); H01L 29/66795 (2013.01); H01L 29/7827 (2013.01); H01L 21/02337 (2013.01); H01L 21/02356 (2013.01);
Abstract

A transistor device that includes a single semiconductor structure having an outer perimeter and a vertical height, wherein the single semiconductor structure is at least partially defined by a trench formed in a semiconductor substrate and a first layer of material positioned on the bottom surface of the trench and around the outer perimeter of the single semiconductor structure. The device also includes a second layer of material positioned on the first layer of material and around the outer perimeter of the single semiconductor structure, a gap between the outer perimeter of the single semiconductor structure and both the first and second layers of material (when considered collectively) and an insulating sidewall spacer positioned in the gap, wherein the insulating sidewall spacer has a vertical height that is less than the vertical height of the single semiconductor structure.


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