The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2022

Filed:

Jun. 27, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Seiyon Kim, Portland, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Anand S. Murthy, Portland, OR (US);

Glenn A. Glass, Portland, OR (US);

Karthik Jambunathan, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/845 (2013.01); H01L 27/088 (2013.01); H01L 27/0886 (2013.01); H01L 27/1211 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/66795 (2013.01); H01L 29/78 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method including forming a fin of a nonplanar device on a substrate, the fin including a second layer between a first layer and a third layer; replacing the second layer with a dielectric material; and forming a gate stack on a channel region of the fin. An apparatus including a first multigate device on a substrate including a fin including a conducting layer on a dielectric layer, a gate stack disposed on the conducting layer in a channel region of the fin, and a source and a drain formed in the fin, and a second multigate device on the substrate including a fin including a first conducting layer and a second conducting layer separated by a dielectric layer, a gate stack disposed the first conducting layer and the second conducting layer in a channel region of the fin, and a source and a drain formed in the fin.


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