The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2022

Filed:

Sep. 10, 2018
Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventors:

Li Hong Xiao, Hubei, CN;

Qian Tao, Hubei, CN;

Yushi Hu, Hubei, CN;

Xiao Tian Cheng, Hubei, CN;

Jian Xu, Hubei, CN;

Haohao Yang, Hubei, CN;

Yue Qiang Pu, Hubei, CN;

Jin Wen Dong, Hubei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 21/762 (2006.01); H01L 21/033 (2006.01); H01L 29/423 (2006.01); H01L 21/308 (2006.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/0337 (2013.01); H01L 21/3086 (2013.01); H01L 21/31144 (2013.01); H01L 21/76229 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 29/40117 (2019.08); H01L 29/42344 (2013.01);
Abstract

A method for forming a three-dimensional memory device includes disposing a material layer over a substrate, forming a plurality of channel-forming holes and a plurality of sacrificial holes around the plurality of channel-forming holes in an array-forming region of the material layer, and forming a plurality of semiconductor channels based on the channel-forming holes and at least one gate line slit (GLS) based on at least one of the plurality of sacrificial holes. A location of the at least one GLS overlaps with the at least one of the plurality of sacrificial holes.


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