The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Dec. 28, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Fei Ma, Chengdu, CN;

Ya ping Chen, Chengdu, CN;

Yunlong Liu, Chengdu, CN;

Hong Yang, Richardson, TX (US);

Shengpin Yang, SiChuan, CN;

Baoqiang Niu, Chengdu, CN;

Rui Liu, Si Chuan, CN;

Zhi Peng Feng, SiChuan, CN;

Seetharaman Sridhar, Richardson, TX (US);

Sunglyong Kim, Allen, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/765 (2006.01); H01L 29/423 (2006.01); H01L 27/24 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/407 (2013.01); H01L 21/765 (2013.01); H01L 21/823487 (2013.01); H01L 27/2454 (2013.01); H01L 29/408 (2013.01); H01L 29/4236 (2013.01); H01L 29/66734 (2013.01); H01L 29/7813 (2013.01); H01L 29/7827 (2013.01);
Abstract

A semiconductor device, and methods of forming the same. In one example, the semiconductor device includes a trench in a substrate having a top surface, and a shield within the trench. The semiconductor device also includes a shield liner between a sidewall of the trench and the shield, and a lateral insulator over the shield contacting the shield liner. The semiconductor device also includes a gate dielectric layer on an exposed sidewall of the trench between the lateral insulator and the top surface. The lateral insulator may have a minimum thickness at least two times thicker than a maximum thickness of the gate dielectric layer.


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