The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2022
Filed:
Jul. 03, 2019
Applied Materials, Inc., Santa Clara, CA (US);
Benjamin Colombeau, San Jose, CA (US);
Tushar Mandrekar, San Jose, CA (US);
Patricia M. Liu, Saratoga, CA (US);
Suketu Arun Parikh, San Jose, CA (US);
Matthias Bauer, Sunnyvale, CA (US);
Dimitri R. Kioussis, San Jose, CA (US);
Sanjay Natarajan, Portland, OR (US);
Abhishek Dube, Fremont, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.