The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2022

Filed:

Nov. 19, 2019
Applicant:

Powertech Technology Inc., Hsinchu County, TW;

Inventors:

Nan-Chun Lin, Hsinchu County, TW;

Hung-Hsin Hsu, Hsinchu County, TW;

Shang-Yu Chang Chien, Hsinchu County, TW;

Wen-Hsiung Chang, Hsinchu County, TW;

Assignee:

Powertech Technology Inc., Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2006.01); H01L 23/48 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 25/04 (2014.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 25/167 (2013.01); H01L 21/4857 (2013.01); H01L 21/561 (2013.01); H01L 21/76898 (2013.01); H01L 23/3121 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/5389 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 25/042 (2013.01); H01L 25/0655 (2013.01); H01L 2224/16221 (2013.01);
Abstract

A semiconductor package including a plurality of first chips, a plurality of through silicon vias, a least one insulator, a first circuit structure and a first encapsulant is provided. The first chip electrically connected to the through silicon vias includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending from the first back surface towards the first active surface. The insulator is disposed on the first active surfaces of the first chips. The first circuit structure disposed on the first back surfaces of the first chips and electrically connected to the through silicon vias. The first encapsulant, laterally encapsulating the first chips.


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