The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

Sep. 02, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Kong-Beng Thei, Pao-Shan Village, TW;

Chien-Chih Chou, New Taipei, TW;

Fu-Jier Fan, Hsinchu, TW;

Hsiao-Chin Tuan, Judong County, TW;

Yi-Huan Chen, Hsin Chu, TW;

Alexander Kalnitsky, San Francisco, CA (US);

Yi-Sheng Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 21/8238 (2006.01); H01L 29/51 (2006.01); H01L 27/092 (2006.01); H01L 27/02 (2006.01); H01L 27/04 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 21/82345 (2013.01); H01L 21/823437 (2013.01); H01L 21/823462 (2013.01); H01L 21/823828 (2013.01); H01L 21/823857 (2013.01); H01L 27/02 (2013.01); H01L 27/0203 (2013.01); H01L 27/04 (2013.01); H01L 27/092 (2013.01); H01L 29/42364 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 27/0922 (2013.01);
Abstract

The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage region and a high voltage region are integrated in a substrate. A low voltage transistor device is disposed in the low voltage region and comprises a low voltage gate electrode and a low voltage gate dielectric separating the low voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage gate electrode and the low voltage gate dielectric. A high voltage transistor device is disposed in the high voltage region and comprises a high voltage gate electrode disposed on the first interlayer dielectric layer.


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