The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

Feb. 28, 2019
Applicant:

Invensas Corporation, San Jose, CA (US);

Inventors:

Hong Shen, Palo Alto, CA (US);

Charles G. Woychik, San Jose, CA (US);

Arkalgud R. Sitaram, Cupertino, CA (US);

Guilian Gao, San Jose, CA (US);

Assignee:

Invensas Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/56 (2006.01); H01L 25/16 (2006.01); H01L 23/31 (2006.01); H01L 21/48 (2006.01); H01L 23/538 (2006.01); H01L 23/13 (2006.01); H01L 25/065 (2006.01); H01L 23/10 (2006.01); H01L 23/00 (2006.01); H01L 23/14 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49827 (2013.01); H01L 21/486 (2013.01); H01L 21/56 (2013.01); H01L 23/10 (2013.01); H01L 23/13 (2013.01); H01L 23/3107 (2013.01); H01L 23/3121 (2013.01); H01L 23/49838 (2013.01); H01L 23/5384 (2013.01); H01L 23/5389 (2013.01); H01L 24/97 (2013.01); H01L 25/0652 (2013.01); H01L 25/162 (2013.01); H01L 23/147 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 25/0655 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/92125 (2013.01); H01L 2224/92225 (2013.01); H01L 2224/97 (2013.01); H01L 2924/157 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15788 (2013.01); H01L 2924/167 (2013.01); H01L 2924/16195 (2013.01); H01L 2924/16788 (2013.01); H01L 2924/181 (2013.01);
Abstract

An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.


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