The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2022

Filed:

May. 14, 2020
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Paul Ganitzer, Finkenstein, AT;

Carsten von Koblinski, Villach, AT;

Thomas Feil, Villach, AT;

Gerald Lackner, Arnoldstein, AT;

Jochen Mueller, Regensburg, DE;

Martin Poelzl, Ossiach, AT;

Tobias Polster, Villach, AT;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/8234 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/495 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 25/065 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8234 (2013.01); H01L 21/561 (2013.01); H01L 21/762 (2013.01); H01L 21/76873 (2013.01); H01L 21/78 (2013.01); H01L 23/481 (2013.01); H01L 23/49562 (2013.01); H01L 25/0655 (2013.01); H01L 23/3114 (2013.01); H01L 23/3135 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/16245 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/73257 (2013.01); H01L 2924/181 (2013.01);
Abstract

In an embodiment, a composite semiconductor substrate includes a first polymer layer and a plurality of semiconductor dies having a first surface, a second surface opposing the first surface, side faces extending between the first surface and the second surface and a first metallization structure on the first surface. Edge regions of the first surface and at least portions of the side faces are embedded in the first polymer layer. At least one metallic region of the first metallization structure is exposed from the first polymer layer. A second metallization structure is arranged on the second surface of the plurality of semiconductor dies. A second polymer layer is arranged on edge regions of the second surface of the plurality of semiconductor dies and on the first polymer layer in regions between the side faces of neighbouring ones of the plurality of semiconductor dies.


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