The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2022

Filed:

Apr. 06, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Huimei Zhou, Albany, NY (US);

Ruqiang Bao, Niskayuna, NY (US);

Michael P. Belyansky, Halfmoon, NY (US);

Andrew M. Greene, Slingerlands, NY (US);

Gen Tsutsui, Glenmont, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/94 (2006.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 21/8238 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7856 (2013.01); H01L 21/0228 (2013.01); H01L 21/28088 (2013.01); H01L 21/762 (2013.01); H01L 21/823821 (2013.01); H01L 29/0649 (2013.01); H01L 29/0673 (2013.01); H01L 29/4966 (2013.01);
Abstract

A method of controlling threshold voltage shift that includes forming a first set of channel semiconductor regions on a first portion of a substrate, and forming a second set of channel semiconductor regions on a second portion of the substrate. A gate structure is formed on the first set of channel semiconductor regions and the second set of channel, wherein the gate structure extends from a first portion of the substrate over an isolation region to a second portion of the substrate. A gate cut region is formed in the gate structure over the isolation region. An oxygen scavenging metal containing layer is formed on sidewalls of the gate cut region.


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