The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 22, 2022

Filed:

Aug. 16, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tsung-Hsi Yang, Zhubei, TW;

Ming-Hua Yu, Hsinchu, TW;

Jeng-Wei Yu, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/167 (2006.01);
U.S. Cl.
CPC ...
H01L 29/105 (2013.01); H01L 29/0847 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/167 (2013.01);
Abstract

A method of forming a semiconductor device includes depositing a p-type semiconductor layer over a portion of a semiconductor substrate, depositing a semiconductor layer over the p-type semiconductor layer, wherein the semiconductor layer is free from p-type impurities, forming a gate stack directly over a first portion of the semiconductor layer, and etching a second portion of the semiconductor layer to form a trench extending into the semiconductor layer. At least a surface of the p-type semiconductor layer is exposed to the trench. A source/drain region is formed in the trench. The source/drain region is of n-type.


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