The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2022

Filed:

Jul. 17, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yi-Tse Hung, Hsinchu, TW;

Chao-Ching Cheng, Hsinchu, TW;

Tse-An Chen, Taoyuan, TW;

Hung-Li Chiang, Taipei, TW;

Lain-Jong Li, Hsinchu, TW;

Tzu-Chiang Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 21/306 (2006.01); H01L 21/28 (2006.01); H01L 29/06 (2006.01); H01L 21/02 (2006.01); B82Y 40/00 (2011.01);
U.S. Cl.
CPC ...
H01L 21/823437 (2013.01); H01L 21/02568 (2013.01); H01L 21/28132 (2013.01); H01L 21/30604 (2013.01); H01L 29/0649 (2013.01); H01L 29/0669 (2013.01); H01L 29/785 (2013.01); H01L 29/7831 (2013.01); B82Y 40/00 (2013.01);
Abstract

In an embodiment, a device includes: a dielectric fin on a substrate; a low-dimensional layer on the dielectric fin, the low-dimensional layer including a source/drain region and a channel region; a source/drain contact on the source/drain region; and a gate structure on the channel region adjacent the source/drain contact, the gate structure having a first width at a top of the gate structure, a second width at a middle of the gate structure, and a third width at a bottom of the gate structure, the second width being less than each of the first width and the third width.


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