The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2022

Filed:

Jul. 08, 2019
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Hai Tao Liu, Singapore, SG;

Li Li Ding, Singapore, SG;

Yao-Hung Liu, Tainan, TW;

Guoan Du, Singapore, SG;

Qi Lu Li, Singapore, SG;

Chunlei Wan, Singapore, SG;

Yi Yu Lin, Singapore, SG;

Yuchao Chen, Singapore, SG;

Huakai Li, Singapore, SG;

Hung-Yueh Chen, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 45/146 (2013.01); H01L 27/2463 (2013.01); H01L 45/08 (2013.01); H01L 45/124 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/1633 (2013.01);
Abstract

The present invention relates to a structure of a memory device. The structure of a memory device includes a substrate, including a bottom electrode layer formed therein. A buffer layer is disposed on the substrate, in contact with the bottom electrode layer. A resistive layer surrounds a whole sidewall of the buffer layer, and extends upward vertically from the substrate. A mask layer is disposed on the buffer layer and the resistive layer. A noble metal layer is over the substrate, and fully covers the resistive layer and the mask layer. A top electrode layer is disposed on the noble metal layer.


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