The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2022

Filed:

Apr. 23, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chun Hsiung Tsai, Xinpu Township, TW;

Clement Hsingjen Wann, Carmel, NY (US);

Kuo-Feng Yu, Zhudong Township, TW;

Yi-Tang Lin, Hsinchu, TW;

Yu-Ming Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/417 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66818 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 29/0649 (2013.01); H01L 29/0673 (2013.01); H01L 29/41791 (2013.01); H01L 29/42392 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01);
Abstract

In a method of manufacturing a semiconductor device including a field effect transistor (FET), a sacrificial region is formed in a substrate, and a trench is formed in the substrate. A part of the sacrificial region is exposed in the trench. A space is formed by at least partially etching the sacrificial region, an isolation insulating layer is formed in the trench and the space, and a gate structure and a source/drain region are formed. An air spacer is formed in the space under the source/drain region.


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