The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2022

Filed:

Dec. 30, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Po-Chih Chen, Hsinchu, TW;

Jiun-Lei Yu, Hsinchu County, TW;

Yao-Chung Chang, Hsinchu County, TW;

Chun-Lin Tsai, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/205 (2006.01); H01L 21/02 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7787 (2013.01); H01L 21/02617 (2013.01); H01L 29/1054 (2013.01); H01L 29/205 (2013.01); H01L 29/66462 (2013.01); H01L 29/2003 (2013.01); H01L 29/4236 (2013.01);
Abstract

The present disclosure provides a semiconductor device comprising a substrate; a first III-V compound layer over the substrate; a second III-V compound layer on the first III-V compound layer; a third III-V compound layer on the second III-V compound layer; a source region on the third III-V compound layer; a drain region on the third III-V compound layer; a first dielectric layer arranged on the second III-V compound layer through the third III-V compound layer; and a gate region on the first dielectric layer, wherein a bottom of the gate region is higher than a top surface of the first dielectric layer; the second lateral distance is larger than the first lateral distance.


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