The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2022

Filed:

Jul. 13, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yi-Hsiang Chao, New Taipei, TW;

Min-Hsiu Hung, Tainan, TW;

Chun-Wen Nieh, Zhubei, TW;

Ya-Huei Li, Tainan, TW;

Yu-Hsiang Liao, Hsinchu, TW;

Li-Wei Chu, New Taipei, TW;

Kan-Ju Lin, Kaohsiung, TW;

Kuan-Yu Yeh, Taoyuan, TW;

Chi-Hung Chuang, Changhua County, TW;

Chih-Wei Chang, Hsin-Chu, TW;

Ching-Hwanq Su, Tainan, TW;

Hung-Yi Huang, Hsin-chu, TW;

Ming-Hsing Tsai, Chu-Pei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 29/45 (2006.01); H01L 21/324 (2006.01); H01L 29/66 (2006.01); H01L 21/285 (2006.01); H01L 21/265 (2006.01); H01L 23/535 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76889 (2013.01); H01L 21/26513 (2013.01); H01L 21/28518 (2013.01); H01L 21/324 (2013.01); H01L 21/76805 (2013.01); H01L 21/76843 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/45 (2013.01); H01L 29/66795 (2013.01); H01L 29/7848 (2013.01); H01L 29/7851 (2013.01);
Abstract

A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.


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