The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2022

Filed:

Jun. 05, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yi Yang, Fremont, CA (US);

Dongna Shen, San Jose, CA (US);

Zhongjian Teng, Santa Clara, CA (US);

Jesmin Haq, Milpitas, CA (US);

Yu-Jen Wang, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 43/12 (2006.01); H01L 43/08 (2006.01); G11C 11/16 (2006.01); H01L 43/02 (2006.01); B82Y 25/00 (2011.01);
U.S. Cl.
CPC ...
H01L 43/12 (2013.01); G11C 11/161 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); B82Y 25/00 (2013.01);
Abstract

A metal layer and first dielectric hard mask are deposited on a bottom electrode. These are patterned and etched to a first pattern size. The patterned metal layer is trimmed using IBE at an angle of 70-90 degrees wherein the metal layer is reduced to a second pattern size smaller than the first pattern size. A dielectric layer is deposited surrounding the patterned metal layer and polished to expose a top surface of the patterned metal layer to form a via connection to the bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. The MTJ stack is etched to a pattern size larger than the via size wherein an over etching is performed. Re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.


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