The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 2021

Filed:

Jan. 17, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shih-Ya Huang, Hsinchu, TW;

Chung-Hao Tsai, Changhua County, TW;

Chen-Hua Yu, Hsinchu, TW;

Chuei-Tang Wang, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 21/56 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 21/4857 (2013.01); H01L 21/56 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 24/16 (2013.01); H01L 25/50 (2013.01); H01L 2224/16146 (2013.01);
Abstract

A passive device module includes a first tier, a second tier and connective terminals. The first tier includes a first semiconductor chip and a first encapsulant. The first semiconductor chip has contact posts. The encapsulant encapsulates the first semiconductor chip. The second tier is disposed on the first tier, and includes a second semiconductor chip, through interlayer walls, and a second encapsulant. The through interlayer walls are locate beside and face sidewalls of the second semiconductor chip and are electrically connected to the contact posts. The second encapsulant encapsulates the second semiconductor chip and the through interlayer walls. The connective terminals are disposed over the second tier and are electrically connected to the first semiconductor chip via the through interlayer walls. The first and second semiconductor chips include passive devices.


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