The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 2021

Filed:

Jul. 08, 2020
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Tao Wang, Wuhan, CN;

Si Ping Hu, Wuhan, CN;

Jia Wen Wang, Wuhan, CN;

Shi Qi Huang, Wuhan, CN;

Jifeng Zhu, Wuhan, CN;

Jun Chen, Wuhan, CN;

Zi Qun Hua, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 23/53238 (2013.01); H01L 21/76841 (2013.01); H01L 23/5384 (2013.01); H01L 24/06 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 27/1157 (2013.01); H01L 27/11582 (2013.01);
Abstract

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. At least one first interconnect is a first dummy interconnect. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. At least one second interconnect is a second dummy interconnect. The second semiconductor structure further includes a second bonding layer including second bonding contacts. Each second interconnect is in contact with a respective second bonding contact. The semiconductor device further includes a bonding interface between the first and second bonding layers. Each first bonding contact is in contact with a respective second bonding contact at the bonding interface.


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