The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 07, 2021
Filed:
Mar. 17, 2020
Globalfoundries U.s. Inc., Santa Clara, CA (US);
Siva P. Adusumilli, South Burlington, VT (US);
Cameron Luce, Colchester, VT (US);
Ramsey Hazbun, Colchester, VT (US);
Mark Levy, Williston, VT (US);
Anthony K. Stamper, Williston, VT (US);
Alvin J. Joseph, Williston, VT (US);
GLOBALFOUNDRIES U.S. INC., Santa Clara, CA (US);
Abstract
Methods of forming structures with electrical isolation. A dielectric layer is formed over a semiconductor substrate, openings are patterned in the dielectric layer that extend to the semiconductor substrate, and a semiconductor material is epitaxially grown from portions of the semiconductor substrate that are respectively exposed inside the openings. The semiconductor material, during growth, defines a semiconductor layer that includes first portions respectively coincident with the openings and second portions that laterally grow from the first portions to merge over a top surface of the dielectric layer. A modified layer containing a trap-rich semiconductor material is formed in the semiconductor substrate.