The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2021

Filed:

May. 30, 2019
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Joachim Hirschler, Villach, AT;

Georg Ehrentraut, Villach, AT;

Christoffer Erbert, St. Magdalen, AT;

Klaus Goeschl, Klagenfurth, AT;

Markus Heinrici, Villach, AT;

Michael Hutzler, Villach, AT;

Wolfgang Koell, Ledenitzen, AT;

Stefan Krivec, Arnoldstein, AT;

Ingmar Neumann, Villach, AT;

Mathias Plappert, Drobollach, AT;

Michael Roesner, Villach, AT;

Olaf Storbeck, Dresden, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 21/18 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02252 (2013.01); H01L 21/0214 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/187 (2013.01); H01L 21/28079 (2013.01); H01L 21/28194 (2013.01); H01L 29/495 (2013.01); H01L 29/51 (2013.01); H01L 29/518 (2013.01);
Abstract

In one aspect, a method of forming a silicon-insulator layer is provided. The method includes arranging a silicon structure in a plasma etch process chamber and applying a plasma to the silicon structure in the plasma etch process chamber at a temperature of the silicon structure equal to or below 100° C. The plasma includes a component and a halogen derivate, thereby forming the silicon-insulator layer. The silicon-insulator layer includes silicon and the component. In another aspect, a semiconductor device is provided having a silicon-insulator layer formed by the method.


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