The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2021

Filed:

Feb. 10, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chia-Hao Chang, Hsinchu, TW;

Sheng-Tsung Wang, Hsinchu, TW;

Lin-Yu Huang, Hsinchu, TW;

Chia-Lin Chuang, Taoyuan, TW;

Cheng-Chi Chuang, New Taipei, TW;

Yu-Ming Lin, Hsinchu, TW;

Chih-Hao Wang, Baoshan Township, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 21/764 (2006.01); H01L 23/522 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/762 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/764 (2013.01); H01L 21/76224 (2013.01); H01L 29/0847 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 21/02271 (2013.01); H01L 21/31116 (2013.01);
Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure includes a gate stack wrapping around a first upper portion of the fin. The semiconductor device structure includes a first stressor and a second stressor respectively over opposite first sides of the fin. The semiconductor device structure includes a spacer structure between the gate stack and the first stressor. The semiconductor device structure includes a first spacer layer covering a sidewall of the gate stack, the spacer structure, and the first stressor. The semiconductor device structure includes a dielectric layer over the first spacer layer. The semiconductor device structure includes an etch stop layer between the first spacer layer and the dielectric layer. The semiconductor device structure includes a seal structure between the second upper portion and the third upper portion.


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