The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2021

Filed:

Mar. 20, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Jiun-Yi Wu, Taoyuan, TW;

Chien-Hsun Lee, Hsin-chu County, TW;

Shou-Yi Wang, Hsinchu, TW;

Chien-Hsun Chen, Pingtung County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 21/52 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5384 (2013.01); H01L 21/52 (2013.01); H01L 21/563 (2013.01); H01L 23/3121 (2013.01); H01L 24/05 (2013.01); H01L 25/0655 (2013.01); H01L 2224/02372 (2013.01);
Abstract

A package has a first semiconductor die, a second semiconductor die, a redistribution structure and a metallic bolstering pattern. The second semiconductor die is disposed beside the first semiconductor die and spaced apart from the first semiconductor die with a distance. The redistribution structure is disposed over the first semiconductor die and the second semiconductor die and is electrically connected with the first and second semiconductor dies. The metallic bolstering pattern is disposed between the redistribution structure and the first and second semiconductor dies. The metallic bolstering pattern is disposed on the redistribution structure and located over the first and second semiconductor dies, and the metallic bolstering pattern extends across the distance between the first and second semiconductor dies and extends beyond borders of the first and second semiconductor dies.


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