The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2021

Filed:

Sep. 30, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Charles H. Wallace, Portland, OR (US);

Marvin Y. Paik, Portland, OR (US);

Hyunsoo Park, Portland, OR (US);

Mohit K. Haran, Hillsboro, OR (US);

Alexander F. Kaplan, Portland, OR (US);

Ruth A. Brain, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76816 (2013.01); H01L 21/31144 (2013.01); H01L 21/76808 (2013.01); H01L 21/76897 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01);
Abstract

Methods and architectures for IC interconnect trenches, and trench plugs that define separations between two adjacent trench ends. Plugs and trenches may be defined through a multiple patterning process. An upper grating pattern may be summed with a plug keep pattern into a pattern accumulation layer. The pattern accumulation layer may be employed to define plug masks. A lower grating pattern may then be summed with the plug masks to define a pattern in trench ILD material, which can then be backfilled with interconnect metallization. As such, a complex damascene interconnect structure can be fabricated at the scaled-down geometries achievable with pitch-splitting techniques. In some embodiments, the trenches are located at spaces between first spacer masks defined in a patterning process associated with the first grating pattern while the plug masks are located based on a tone-inversion of second spacer masks associated with the second grating pattern.


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