The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 2021
Filed:
Oct. 24, 2019
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Po-Hsiang Huang, Tainan, TW;
Chin-Chou Liu, Jhubei, TW;
Sheng-Hsiung Chen, Zhubei, TW;
Fong-Yuan Chang, Hsinchu, TW;
Hui-Zhong Zhuang, Kaohsiung, TW;
Meng-Hsueh Wang, Hsinchu, TW;
Yi-Kan Cheng, Taipei, TW;
Chun-Chen Chen, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A method of generating a layout diagram including a first level of metallization (M_1st level) including: identifying, in the layout diagram, a filler cell and a first functional cell substantially abutting the filler cell; the first functional cell including first and second side boundaries, first wiring patterns in the M_1st level, and representing corresponding first conductors in the first functional cell region; and first and second groups of cut patterns overlying corresponding portions of the first wiring patterns and being substantially aligned with the corresponding first and second side boundaries; adjusting one or more locations of corresponding one or more selected cut patterns of the second group thereby correspondingly elongating one or more selected ones of the first wiring patterns so as to be corresponding first elongated wiring patterns which extend across the second boundary of the first functional cell into the filler cell.