The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2021

Filed:

Jan. 07, 2020
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

XinRu Zeng, Wuhan, CN;

Peng Chen, Wuhan, CN;

Houde Zhou, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 25/00 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/56 (2013.01); H01L 23/3121 (2013.01); H01L 23/3135 (2013.01); H01L 23/5384 (2013.01); H01L 24/05 (2013.01); H01L 25/50 (2013.01);
Abstract

A chip package structure including a first chip stack and a redistribution layer is provided. The first chip stack includes a plurality of first chips, a first molding layer and at least one first vertical conductive element. The plurality of first chips are sequentially stacked, wherein each of the plurality of first chips includes at least one first bonding pad, and the first bonding pads are not covered by the plurality of first chips. The first molding layer encapsulates the plurality of first chips. The at least one first vertical conductive element penetrates through the first molding layer, wherein the at least one first vertical conductive element is disposed on and electrically connected to at least one of the first bonding pads. The redistribution layer is disposed on the first chip stack and electrically connected to the at least one first vertical conductive element.


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