Nanosheet device with tall suspension and tight contacted gate poly-pitch

Abstract

A nanosheet FET has a substrate, an insulating layer disposed on the substrate, a source disposed on the insulating layer, and a drain disposed on the insulting layer. A plurality of parallel channels electrically and physically connects to and between the source and drain. One or more of the channels is separated from one or more adjacent and parallel channels by a suspension distance with two inner spacers. The inner spacers have three parts: a lower inner spacer, a middle inner spacer, and an upper inner spacer. The inner spacer design enables making the inner spacer using thinner layers of deposited dielectric material. The thinner deposition layers do not close the device spacing as much and enable smaller CPP while maintaining taller suspension distances.