The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2021

Filed:

Oct. 28, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Eric C. Harley, Lagrangeville, NY (US);

Judson R. Holt, Wappingers Falls, NY (US);

Yue Ke, Fishkill, NY (US);

Rishikesh Krishnan, Poughkeepsie, NY (US);

Keith H. Tabakman, Newburgh, NY (US);

Henry K. Utomo, Newburgh, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 27/0924 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/1608 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A device and method for forming a semiconductor device includes forming a gate structure on a channel region of fin structures and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.


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