The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2021

Filed:

Feb. 01, 2019
Applicant:

Dialog Semiconductor (Uk) Limited, London, GB;

Inventors:

Ernesto Gutierrez, III, Swindon, GB;

Jesus Mennen Belonio, Jr., Neubiberg, DE;

Eric Hu, Taichung, TW;

Melvin Martin, Stuttgart, DE;

Jerry Li, Taichung, TW;

Francisco Vergara Cadacio, Germering, DE;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 25/16 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 21/481 (2013.01); H01L 21/4853 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 24/20 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 24/96 (2013.01); H01L 25/0657 (2013.01); H01L 25/16 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/9211 (2013.01);
Abstract

A substrate is provided having a top side and a bottom side, having redistribution layers therein, having at least one copper pillar connected to the redistribution layers on the top side and at least one copper pillar connected to the redistribution layers on the bottom side, and having at least one cavity extending partially into the bottom side of the substrate. At least one passive component is mounted onto the copper pillar on the top side and embedded in a molding compound. At least one silicon die is mounted in the cavity wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers. At least one solder ball is mounted on the at least one copper pillar on the bottom side of the substrate to provide package output.


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