The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2021

Filed:

Mar. 30, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Lisa Ying Ying Chen, Chandler, AZ (US);

Lauren Ashley Link, Tempe, AZ (US);

Robert Alan May, Chandler, AZ (US);

Amruthavalli Pallavi Alur, Tempe, AZ (US);

Kristof Kuwawi Darmawikarta, Chandler, AZ (US);

Siddharth K. Alur, Chandler, AZ (US);

Sri Ranga Sai Boyapati, Chandler, AZ (US);

Andrew James Brown, Phoenix, AZ (US);

Lilia May, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/15 (2006.01); C04B 35/622 (2006.01); C04B 35/64 (2006.01); H01L 23/498 (2006.01); G03F 7/16 (2006.01); G03F 7/20 (2006.01); G03F 7/32 (2006.01);
U.S. Cl.
CPC ...
H01L 23/15 (2013.01); C04B 35/62218 (2013.01); C04B 35/64 (2013.01); H01L 21/486 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); C04B 2235/48 (2013.01); C04B 2235/6026 (2013.01); G03F 7/16 (2013.01); G03F 7/2002 (2013.01); G03F 7/322 (2013.01); H01L 23/49816 (2013.01);
Abstract

Semiconductor packages including package substrates having polymer-derived ceramic cores are described. In an example, a package substrate includes a core layer including a polymer-derived ceramic. The polymer-derived ceramic may include filler particles to control shrinkage and reduce warpage of the core layer during fabrication and use of the package substrate. The core layer may include counterbores or blind holes to embed a contact pad or an electrical interconnect in the core layer. A semiconductor die may be mounted on the package substrate and may be electrically connected to the contact pad or the electrical interconnect.


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