The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 2021

Filed:

Jul. 22, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Jyuh-Fuh Lin, Miaoli County, TW;

Cheng-Hung Chen, Hsinchu County, TW;

Pei-Yi Liu, Changhua County, TW;

Wen-Chuan Wang, Hsinchu, TW;

Shy-Jay Lin, Hsinchu County, TW;

Burn Jeng Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 1/36 (2012.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); H01L 27/02 (2006.01); H01L 21/762 (2006.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
G03F 1/36 (2013.01); G06F 30/39 (2020.01); G06F 30/392 (2020.01); H01L 27/0207 (2013.01); G06F 2119/18 (2020.01); H01L 21/76229 (2013.01); H01L 27/0203 (2013.01);
Abstract

The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio rto optimize a uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for dummy features and adding the dummy features in the IC design layout.


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