The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 2021

Filed:

Feb. 20, 2017
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Olivier Joubert, Meylan, FR;

Jason A. Kenney, Sunnyvale, CA (US);

Sunil Srinivasan, Milpitas, CA (US);

James Rogers, Los Gatos, CA (US);

Rajinder Dhindsa, Pleasanton, CA (US);

Vedapuram S. Achutharaman, Saratoga, CA (US);

Olivier Luere, Sunnyvale, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/687 (2006.01); H01J 37/32 (2006.01); H01L 21/683 (2006.01);
U.S. Cl.
CPC ...
H01L 21/68735 (2013.01); H01J 37/32623 (2013.01); H01J 37/32642 (2013.01); H01J 37/32715 (2013.01); H01L 21/6833 (2013.01); H01J 37/32082 (2013.01); H01J 2237/334 (2013.01); H01J 2237/3321 (2013.01);
Abstract

The implementations described herein generally relate to a process kit suitable for use in a semiconductor process chamber, which reduces edge effects and widens the processing window with a single edge ring as compared to conventional process kits. The process kit generally includes an edge ring disposed adjacent to and surrounding a perimeter of a semiconductor substrate in a plasma chamber. A dimension of a gap between the substrate and the edge ring is less than about 1000 μm, and a height difference between the substrate and the edge ring is less than about (+/−) 300 μm. The resistivity of the ring is less than about 50 Ohm-cm.


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