The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2021

Filed:

May. 25, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yi-Hsiu Chen, Hsinchu, TW;

Chen-Hua Yu, Hsinchu, TW;

Ming-Fa Chen, Taichung, TW;

Wen-Chih Chiou, Miaoli County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 25/00 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 21/683 (2006.01); H01L 21/66 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 21/31058 (2013.01); H01L 21/31144 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/6835 (2013.01); H01L 24/89 (2013.01); H01L 24/94 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); H01L 21/78 (2013.01); H01L 22/32 (2013.01); H01L 24/08 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68327 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/13101 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/80801 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/1304 (2013.01); H01L 2924/1433 (2013.01);
Abstract

A method of manufacturing a semiconductor package structure includes: bonding a die to a wafer; forming a dielectric material layer on the wafer to cover a top surface and sidewalls of the die; performing a removal process to remove a portion of the dielectric material layer, so as to at least expose a portion of the top surface of the die, wherein the dielectric material layer comprises a protruding part over the top surface of the die after performing the removal process; and performing a planarization process to planarize top surfaces of the die and the dielectric material layer, and thereby forming a dielectric layer laterally aside the die.


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