The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 2021
Filed:
Feb. 10, 2012
Applicants:
Chen-hua Yu, Hsin-Chu, TW;
Cheng-hung Chang, Hsin-Chu, TW;
Chen-nan Yeh, Hsi-Chih, TW;
Yu-rung Hsu, Tainan, TW;
Inventors:
Chen-Hua Yu, Hsin-Chu, TW;
Cheng-Hung Chang, Hsin-Chu, TW;
Chen-Nan Yeh, Hsi-Chih, TW;
Yu-Rung Hsu, Tainan, TW;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/7843 (2013.01); H01L 29/20 (2013.01); H01L 2029/7858 (2013.01);
Abstract
System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.